general description the max3772?ax3775 are dual-rate (1.0625gbps and 2.125gbps) fibre channel repeaters. they are opti- mized for use in fibre channel arbitrated loop applica- tions and operate from a +3.3v supply. the max3772?ax3775 exceed fibre channel jitter toler- ance requirements and can recover data signals with up to 0.7 unit interval (ui) jitter. the circuit? fully inte- grated phase-locked loop (pll) provides a frequency lock indication and does not need an external reference clock. these repeaters provide low-jitter cml clock and data outputs, and are pin compatible with the max3770 repeater (except ratesel pin and exposed paddle). the max3773/max3774 can also be used for imped- ance transformation between 100 ? (differential) and 150 ? (differential) systems. to reduce the number of external components, all signal inputs and outputs are internally terminated. the max3772?ax3775 are available in 16-pin qsop-ep packages. applications 1.0625gbps/2.125gbps dual-rate fibre channel fibre channel data storage systems storage area networks fibre channel hubs 100 ? /150 ? (differential) impedance transformation features pin selectable 1.0625gbps/2.125gbps dual-rate fibre channel operation exceeds fibre channel jitter tolerance requirements 1400mv differential output swing +3.0v to +3.6v operation no reference clock required frequency lock indication 290mw power consumption (max3775) at +3.3v 100 ? /150 ? (differential) input/output terminations max3772?ax3775 dual-rate fibre channel repeaters ________________________________________________________________ maxim integrated products 1 ordering information 3.3v z o = 75 ? port bypass circuit fibre channel repeater z o = 75 ? max3775 clk+ clk- gnd ratesel clken v cc 0.047 f 0.1 f out+ out- in+ in- cf- cf+ lock 3.3v max3750 gnd sel v cc gnd sel v cc 0.1 f out+ out- in+ in- lin+ lin- lout- lout+ lin+ lin- lout- lout+ port bypass circuit 3.3v max3750 0.1 f out+ out- in+ in- z o = 75 ? z o = 75 ? typical operating circuits 19-2192; rev 0; 10/01 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pin configuration appears at end of data sheet. selector guide appears at end of data sheet. part temp. range pin-package max3772 cee 0 c to +70 c 16 qsop-ep max3773 cee 0 c to +70 c 16 qsop-ep max3774 cee 0 c to +70 c 16 qsop-ep max3775 cee 0 c to +70 c 16 qsop-ep
max3772?ax3775 dual-rate fibre channel repeaters 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v cc = +3.0v to +3.6v, 8b/10b data coding, c f = 0.047f, lock pin loaded with 15k ? resistor, all high-speed inputs and outputs ac-coupled, t a = 0 c to +70 c, unless otherwise noted. typical values are at v cc = +3.3v, t a = +25 c.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc ........................................................................-0.5v to +5.0v pin voltage levels (in, cf, ratesel, clken, lock) .....................-0.5v to (v cc + 0.5v) current into lock...............................................-1ma to +10ma cml output currents (out, clk), r out = 75 ? ........ +22ma cml output currents (out, clk), r out = 50 ? ........ +33ma continuous power dissipation (t a = +70 c) 16-pin qsop-ep (derate 18.9mw/ c above +70 c) ...702mw operating junction temperature range ...........-55 c to +150 c operating temperature range .........................-55 c to +110 c storage temperature range ............................-55 c to +150 c lead temperature (soldering, 10s) ................................+300 c parameter conditions min typ max units max3772/max3773 80 101 140 clken = gnd max3774/max3775 68 88 124 max3772/max3773 115 146 195 supply current (note 1) clken = v cc max3774/max3775 95 121 164 ma max3772/max3773, 100 ? terminated 1000 1400 1800 differential voltage signal at out + figure 1 max3774/max3775, 150 ? terminated 1000 1400 1800 mvp-p max3772/max3773 100 ? terminated 1000 1400 1800 differential voltage signal at clk + figure 1 max3774/max3775, 150 ? terminated 1000 1400 1800 mvp-p 1.0625gbps operation, ratesel = gnd -100 +100 input data rate range 2.125gbps operation, ratesel = v cc -100 +100 ppm 20% to 80% 1.0625gbps operation 136 325 input edge speed 20% to 80% 2.125gbps operation 75 160 ps data transition time (out) 20% to 80% (note 2) 100 130 175 ps clock transition time (clk) 20% to 80% (note 2) 50 75 100 ps lock output low i ol = +250a (sinking) 0.4 v lock output high i oh = -100a (sourcing) 2.4 v clken, ratesel input current -50 50 a clken, ratesel input low -0.3 0.8 v clken, ratesel input high 2 v cc + 0.3 v differential input voltage swing 200 2200 mvp-p input common-mode voltage v cc - 0.45 v differential voltage across cf + (note 2) v cc v cdr lock time input = cjtpat (note 3) 500 s
max3772?ax3775 dual-rate fibre channel repeaters _______________________________________________________________________________________ 3 electrical characteristics (continued) (v cc = +3.0v to +3.6v, 8b/10b data coding, c f = 0.047f, lock pin loaded with 15k ? resistor, all high-speed inputs and outputs ac-coupled, t a = 0 c to +70 c, unless otherwise noted. typical values are at v cc = +3.3v, t a = +25 c.) parameter conditions min typ max units max3772/max3774 78 100 122 differential input resistance (in + ) max3773/max3775 118 150 182 ? max3772/max3773 78 100 122 differential output resistance (out + , clk + ) max3774/max3775 118 150 182 ? 10hz f < 100hz 100 100hz f < 1mhz 40 supply noise tolerance (note 4) 1mhz f < 2.5ghz 10 mvp-p operation at 2.125gbps (note 2) input = k28.7 (note 5) 4.4 input = crpat (note 6) 2.8 random jitter generation at out + and clk + input = crpat (notes 6, 7) 2.9 ps rms input = k28.5 (note 8) 22 deterministic jitter on out + input = rpat (notes 7, 9) 48 psp-p total jitter at out + input = rpat (notes 7, 9, 10) 99 psp-p f = 85khz 1.5 f = 1270khz 0.1 sinusoidal component of jitter tolerance (ber = 10 -12 ) input = cjtpat (notes 3, 7) f = 10mhz 0.1 ui total high-frequency jitter tolerance input = cjtpat (notes 3, 7, 9) 0.7 ui jitter transfer bandwidth measured with 50% edge density 11 mhz jitter transfer peaking (note 11) 0.05 db propagation delay 1.0 1.5 ns clock to q delay falling clock to data transition 150 280 300 ps operation at 1.0625gbps (note 2) input = k28.7 (note 5) 6.2 input = crpat (note 6) 3.6 random jitter generation at out + and clk + input = crpat (notes 6, 7) 4.9 ps rms input = k28.5 (note 8) 40 deterministic jitter on out + input = rpat (notes 7, 9) 75 psp-p total jitter at out + input = rpat (notes 7, 9, 10) 160 psp-p f = 42.5khz 1.5 f = 635khz 0.1 sinusoidal component of jitter tolerance (ber = 10 -12 ) input = cjtpat (notes 3, 7) f = 5mhz 0.1 ui total high-frequency jitter tolerance input = cjtpat (notes 3, 7, 9) 0.7 ui jitter transfer bandwidth measured with 50% edge density 6 mhz jitter transfer peaking (note 11) 0.05 db propagation delay 5ns clock to q delay falling clock to data transition 200 510 740 ps
max3772?ax3775 note 1: supply current includes output currents. note 2: guaranteed by design and characterization. note 3: compliant jitter tolerance pattern in hex (cjtpat): pattern sequence: repetitions: 3e aa 2a aa aa 6 3e aa a6 a5 a9 1 87 1e 38 71 e3 41 87 1e 38 70 bc 78 f4 aa aa aa 1 aa aa aa aa aa 12 aa a1 55 55 e3 87 1e 38 71 e1 1 ab 9c 96 86 e6 1 c1 6a aa 9a a6 1 note 4: meets jitter output specifications with noise applied. note 5: k28.7 pattern: 00 1111 1000. note 6: compliant random pattern in hex (crpat): pattern sequence: repetitions: 3e aa 2a aa aa 6 3e aa a6 a5 a9 1 86 ba 6c64 75 d0 e8 dc a8 b4 79 49 ea a6 65 16 72 31 9a 95 ab 1 c1 6a aa 9a a6 1 note 7: parameter measured with 0.40ui deterministic jitter (patterns other than k28.7), and 0.20ui random jitter (ber = 10 - 12 ) applied to the input. jitter is in compliance with the inter-enclosure, fibre channel jitter tolerance (at compliance point r ) and jitter output (at compliance point t ) specifications (fc-pi rev 10.0). output jitter is specified as an output total given a non-zero jitter input. note 8: k28.5 pattern: 00 1111 1010 11 0000 0101 note 9: random pattern in hex (rpat): 3eb0 5c67 85d3 172c a856 d84b b6a6 65 note 10: using differential drive over the entire input amplitude range. the input signal bandwidth is limited to 0.75 x (bit-rate) by a 4th- order bessel thompson filter or equivalent. total jitter (tj) is the range of the eye pattern where the ber exceeds 10 -12 . tj can be estimated as tj = dj + 14 x rj. dj is deterministic jitter. rj is a one sigma distribution (rms) of random jitter. note 11: simulation shows peaking of 0.01db max. characterization results limited by test equipment. dual-rate fibre channel repeaters 4 _______________________________________________________________________________________ electrical characteristics (continued) (v cc = +3.0v to +3.6v, 8b/10b data coding, c f = 0.047f, lock pin loaded with 15k ? resistor, all high-speed inputs and outputs ac-coupled, t a = 0 c to +70 c, unless otherwise noted. typical values are at v cc = +3.3v, t a = +25 c.)
max3772?ax3775 dual-rate fibre channel repeaters _______________________________________________________________________________________ 5 -10 -8 -9 -6 -5 -4 -3 -2 -7 0 -1 1 10k 100k 1m 10m 2.125gbps jitter transfer vs. frequency max3772-75 toc01 frequency (hz) jitter attenuation (db) 200mvp-p input signal, pattern = crpat -10 -8 -9 -6 -5 -4 -3 -2 -7 0 -1 1 10k 100k 1m 10m 1.0625gbps jitter transfer vs. frequency max3772-75 toc02 frequency (hz) jitter attenuation (db) 200mvp-p input signal, pattern = crpat 100 0.1 10k 1m 10m 2.125gbps jitter tolerance 1 10 max3772 toc03 frequency ( hz ) sinusoidal jitter (uip-p) 100k cjtpat pattern, dj = 0.4ui rj = 0.2ui tolerance exceeds the test equipment's generation limit fibre channel mask 100 0.1 10k 1m 10m 1.0625gbps jitter tolerance 1 10 max3772 toc04 frequency (hz) sinusoidal jitter (uip-p) 100k cjtpat pattern, dj = 0.4ui rj = 0.2ui tolerance exceeds the test equipment's generation limit fibre channel mask output eye diagram at out (2.125gbps crpat) max3772-75 toc05 input = 600mv dj = 0.4ui rj = 0.2ui max3772-75 toc06 output eye diagram at out (1.0625gbps crpat) input = 600mv dj = 0.4ui rj = 0.2ui 1e-12 1e-10 1e-11 1e-09 1e-08 1e-07 1e-06 1e-05 1e-04 1e-03 1e-02 1e-01 1e+00 2.125gbps output jitter bathtub plot max3772-75 toc07 data-crossing time relative to first zero crossing (ui) bit error rate 0 0.4 0.2 0.6 0.8 1.0 2.125gbps crpat at input (dj = 0.4ui, rj = 0.2ui) 1e-12 1e-10 1e-11 1e-09 1e-08 1e-07 1e-06 1e-05 1e-04 1e-03 1e-02 1e-01 1e+00 1.0625gbps output jitter bathtub plot max3772-75 toc08 data-crossing time relative to first zero crossing (ui) bit error rate 0 0.4 0.2 0.6 0.8 1.0 1.0625gbps crpat at input (dj = 0.4ui, rj = 0.2ui) typical operating characteristics (v cc = +3.3v, t a = +25 c, unless otherwise noted.)
max3772?ax3775 detailed description figure 2 shows the functional block diagram of the max3772 max3775 fibre channel repeaters. they con- sist of a fully integrated pll, cml input and output buffers, and a data latch. the pll consists of a com- bined phase detector (pd) and frequency detector (fd), a loop filter, and a voltage-controlled oscillator (vco). the input and output signal buffers employ low- noise cml architecture and are terminated on-chip. phase and frequency detector the frequency difference between the vco clock and the received data is derived by sampling the in-phase and quadrature vco outputs on the edges of the input data signal. the fd drives the vco until the frequency difference is reduced to zero. once frequency acquisi- tion is complete, the pd produces a voltage proportion- al to the phase difference between the incoming data and the internal clock. the pll drives this error voltage to zero, aligning the recovered clock to the center of the incoming eye. dual-rate fibre channel repeaters 6 _______________________________________________________________________________________ pin description pin name function 1 cf+ cdr filter capacitor positive connection. c f = 0.047f. 2 cf- cdr filter capacitor negative connection. c f = 0.047f. 3, 6, 12 gnd electrical ground 4 in+ noninverted data input 5 in- inverted data input 7, 8 v cc supply voltage 9 ratesel rate select pin. ttl low selects 1.0625gbps operation. ttl high selects 2.125gbps operation. 10 out- inverted data output 11 out+ noninverted data output 13 clken clock output enable. ttl high enables the clock output. ttl low disables the clock output. 14 clk- inverted clock output. enabled when clken is forced high; disabled when clken is forced low. 15 clk+ noninverted clock output. enabled when clken is forced high; disabled when clken is forced low. 16 lock frequency lock indicator. when data is present, a high level indicates the pll is frequency-locked. the output of the lock pin may chatter when large jitter is applied to the input. ep exposed paddle the exposed paddle must be soldered to the circuit board ground for proper thermal performance. 500mvp-p min 900mvp-p max 1000mvp-p min 1800mvp-p max v out + v out - (v out +) - (v out -) figure 1. example of output signal with matched output loads
loop filter, vco, and latch the phase detector and frequency detector outputs are summed into a loop filter. an external capacitor (between cf+ and cf-) is required to set the pll damping factor. the fully integrated vco contains an internal current reference and filter circuitry to minimize the influence of v cc noise. the vco creates a clock output with frequency proportional to the control volt- age applied by the loop filter. data recovery is accom- plished by using the recovered clock signal to latch the incoming data to the cml output buffers, significantly reducing output jitter. lock output an active high lock output monitor derived from the frequency detector indicates that the pll is frequency- locked onto the input data. without input data, the lock signal may settle high or low. the use of a low- pass rc filter is recommended to reduce the effects of chatter that could be caused by high input-jitter con- tent. for optimum jitter performance, keep the load 15k ? on the output of the lock pin. ratesel input the ratesel input is used to select between input data rates of 2.125gbps and 1.0625gbps. this func- tion allows the repeater to sample data at the correct data rate by selecting a divide-by-2 network, giving maximum jitter tolerance at both data rates. the loop bandwidth of the repeater scales with the selected fre- quency; i.e., the loop-bandwidth at an input rate of 1.0625gbps is half that at the input rate of 2.125gbps. see the applications information section for the func- tionality of the ratesel pin. applications information input and output terminations figures 3 and 4 show models for the max3772 max3775 inputs and outputs, including packaging parasitics. max3772?ax3775 dual-rate fibre channel repeaters _______________________________________________________________________________________ 7 esd structures in+ package 1.5nh 1.5nh 0.2pf 0.4pf 0.4pf v cc - 0.450v 0.2pf optional 50 ? or 75 ? 1k ? v cc figure 3. input structure in+ in- loop filter vco 2 1 0 out+ out- v cc clk+ clk- lock v cc dq ratesel clken cf+ cf- 0.047 f phase/freq detector optional 50 ? or 75 ? optional 100 ? or 150 ? termination figure 2. block diagram
max3772?ax3775 control functions the max3772 max3775 have two control inputs: ratesel and clken. ratesel is an input that sets the operational data rate for the repeaters. table 1 shows the selected input data rates when using the ratesel function. clken is an input that can be used to enable or dis- able the output clock, as shown in table 2. layout procedure the max3772 max3775 performance can be greatly affected by circuit-board layout and design. use good high-frequency design techniques, including minimiz- ing ground inductance and using fixed-impedance transmission lines on the data and clock signals. all in, out, and clk pins should be connected with 0.1f coupling capacitors equivalent or better than x5r. a 0.047f capacitor should be used for the loop filter. if dc coupling is desired pay particular attention to the dc voltage and current requirements at the pins of interest (see dc electrical characteristics ). the max3750/max3754/max3755 port bypass circuits can be dc-coupled to the maxim dual-rate repeaters. the exposed paddle of the repeater must be connected to ground and should be soldered onto the circuit board for optimal thermal and electrical operation. dual-rate fibre channel repeaters 8 _______________________________________________________________________________________ 1.5nh 0.4pf 0.2pf out+ out- 0.4pf 0.2pf 1.5nh esd structures package v cc optional 50 ? or 75 ? figure 4. output structure 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 cf+ lock clk+ clk- clken gnd out+ out- ratesel top view max3772 max3773 max3774 max3775 qsop-ep* *exposed paddle must be soldered to ground. cf- gnd gnd in+ in- v cc v cc pin configuration ratesel level data rate selected gnd 1.0625gbps v cc 2.125gbps clken level clock output gnd disabled v cc enabled table 1. input data rate using ratesel function table 2. clken function chip information transistor count: 1280 process: si selector guide part differential input termination differential output termination max3772 cee 100 ? 100 ? max3773 cee 150 ? 100 ? max3774 cee 100 ? 150 ? max3775 cee 150 ? 150 ?
max3772?ax3775 dual-rate fibre channel repeaters maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 _____________________ 9 ? 2001 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information
|
